An I2C bus is a bi-directional two wire bus that is designed to provide efficient communication between integrated circuit (IC) chips. The expression “I2C” stands for “Inter-Integrated Circuit”. The expression I2C is sometimes written as “I2C” and referred to as “I-squared C”.
An I2C bus comprises two active bi-directional wires and a ground connection. The first wire is a Serial Data line (referred to by the letters SDA). The SDA line carries the data on the I2C bus. The second wire is a Serial Clock line (referred to by the letters SCL). The SCL line carries the clock signals on the I2C bus.
The I2C bus is a multi-master bus. The expression “multi-master” means that more than one integrated circuit (IC) is capable of initiating a data transfer on an I2C bus. An integrated circuit (IC) that initiates a data transfer on an I2C bus is referred to as the Bus Master. During the time that the Bus Master is making a data transfer on the I2C bus, the other integrated circuits (that receive the data transfer) are referred to as Bus Slaves.
The principles of operation of the I2C bus are well known in the art. The operation of the I2C bus is set forth and described in a document entitled I2C Bus Specification (Version 2.1). A data bus that is compatible with the principles of operation of an I2C bus is referred to as an “I2C compatible bus.”
Sometimes an I2C compatible bus is used to communicate with a plurality of integrated circuit chips where some of the integrated circuits chips operate on different values of supply voltage. In such a case the lowest value of supply voltage of the integrated circuit chips is chosen to be the supply voltage Vdd for the I2C compatible bus.
For example, one of the integrated circuit chips on an I2C compatible bus may be a ninety nanometer (90 nm) feature sized central processing unit (CPU) chip that operates with a supply voltage of one volt (1.0 V). Other chips may be one half micron (0.5 μm) feature sized power chips that operate on a supply voltage in the range of three and six tenths volts (3.3 V) to five and five tenths volts (5.5 V). In order not to exceed the maximum voltage of the CPU chip, the system I2C compatible bus supply voltage Vdd is chosen to be one volt (1.0 V).
Selecting the I2C compatible bus supply voltage Vdd to have the lowest value of supply voltage (one volt (1.0 V) in the present example) means that the other integrated circuit chips on the I2C compatible bus that require a higher value of supply voltage must level shift the input signals.
Several types of prior art level shifter circuits exist. FIG. 1 illustrates a circuit diagram of one prior level shifter circuit 100. The level shifter circuit 100 comprises three NMOS transistors (M0, M1, M2) and three PMOS transistors (M3, M4, M5) connected together as shown in FIG. 1. PMOS transistor M4 and NMOS transistor M2 are connected together in an inverter configuration. The input signal (designated with the letters “in”) is provided to the gate of PMOS transistor M4 and to the gate of NMOS transistor M2. The source of PMOS transistor M4 is connected to an input reference voltage Vdd1. The source of NMOS transistor M2 is connected to the negative supply voltage VSS.
PMOS transistor M3 and PMOS transistor M5 are connected in parallel with each of their sources connected to a positive supply voltage Vdd2. The gate of PMOS transistor M3 is connected to the drain of PMOS transistor M5. The gate of PMOS transistor M5 is connected to the drain of PMOS transistor M3. The drain of PMOS transistor M3 is connected to the drain of NMOS transistor M0. The drain of PMOS transistor M5 is connected to the drain of NMOS transistor M1. The source of NMOS transistor M0 and the source of NMOS transistor M1 are each connected to the negative supply voltage VSS.
The input signal “in” is also provided to the gate of NMOS transistor M0. The output of the inverter circuit formed by PMOS transistor M4 and NMOS transistor M2 is provided to the gate of NMOS transistor M1. The output node (designated “out”) of level shifter circuit 100 is connected between the drain of PMOS transistor M5 and the drain of NMOS transistor M1.
The prior art level shifter circuit 100 shown in FIG. 1 performs the level shift function. However, it has a disadvantage in that it requires an additional reference voltage signal Vdd1. It would be desirable to have a level shifter circuit that does not require the use of an additional reference voltage signal.
FIG. 2 illustrates a circuit diagram of another second prior level shifter circuit 200. Level shifter circuit 200 does not require an additional reference voltage signal. However, level shifter circuit 200 does require a standby current. The requirement of a standby current is disadvantageous in that the power consumption of the standby current could be quite significant for large power supply differences and/or high input data rates.
Level shifter circuit 200 comprises three PMOS transistors (M0, M8, M12) and five NMOS transistors (M1, M3, M6, M7, M11) connected together as shown in FIG. 2. NMOS transistor M11 and PMOS transistor M12 are connected together in an inverter configuration. The remaining PMOS transistors (M0 and M8) and the remaining NMOS transistors (M1, M3, M6, and M7) are connected together in a Schmitt trigger configuration.
The prior art level shifter circuit 200 shown in FIG. 2 performs the level shift function. However, it has a disadvantage in that it requires a standby current. It would be desirable to have a level shifter circuit that does not require the use of a standby current.
There is a need in the art for a system and method that can provide an improved level shifter circuit. In particular, there is a need in the art for a system and method that can provide a level shifter circuit that can enable an integrated circuit device to interface with an I2C compatible bus that operates at a power supply voltage that is significantly lower than the power supply voltage of the integrated circuit device.
Before undertaking the Detailed Description of the Invention below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms “include” and “comprise,” as well as derivatives thereof, mean inclusion without limitation; the term “or,” is inclusive, meaning and/or; the phrases “associated with” and “associated therewith,” as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like.
The term “controller” means any device, system, or part thereof that controls at least one operation. A controller may be implemented in hardware, software, firmware, or combination thereof. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely.
Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior uses, as well as to future uses, of such defined words and phrases.